1. Field of the Invention
This invention relates in general to timing and clock systems in integrated electronics, and more particularly to a method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency.
2. Description of Related Art
Many complex integrated circuits, and in particular application specific integrated circuits (ASICs), have multiple variable interfaces to allow for interconnecting different components. For example, an ASIC may include an off-board interface, a processor bus, standard interfaces and memory interfaces. In addition to these interfaces, an ASIC may also include one or more internal clocks which could be asynchronous to all of the interfaces.
However, data may need to be transferred between the interfaces on the chip and across asynchronous boundaries. This creates performance difficulties due to having to use methods to synchronize the data. More importantly this creates tremendous challenges in verifying functionality before the ASIC is sent to a foundry for fabrication. Still further, many external oscillator devices are usually needed to provide all of the different clocks.
For example, an ASIC may include an off-board interface and standard interfaces that are all peripheral component interconnect (PCI-X) interfaces and which are also PCI 2.2 compliant. This implies that the frequency of the clock coming into the ASIC can range from 0 to 1.33 MHz. Depending on loading conditions on each of the standard on board interfaces, the desired frequency to those interfaces may vary. Further, the processor interface may need to operate at a higher frequency, e.g., 200 MHz and a memory may need to operated at 133 MHz. An internal clock may be provided with a separate oscillator operating at 66 MHz. There may also be functional islands to perform compression which need to run at 100 MHz and another functional island to perform encryption which needs to run at 50 MHz. A first standard interface may be a 66 MHz PCI, while a second standard interface may be a PCI-X operating at 133 MHz. Accordingly, the ASIC could require as many as 6 external components and numerous internal phase-locked loops (PLLs) in order to provide all of these signals.
Depending on the implementation, data transfers could span asynchronous boundaries in almost every direction across the clock domains. Since many of the clocks in the example above have a range of valid frequencies, verification becomes very complex. In the above example, there are essentially 6 variables with many different valid values for each variable. Because crossing asynchronous boundaries can introduce timing and logic problems, it is important to do a thorough job in verification to reduce the possibility of having to fabricate the chip another time.
To provide multiple frequency domains as described above, most designs will use multiple oscillators or will fix the relationships between the different clock partitions even though the main bus may provide the main clock. However, using multiple oscillators has the disadvantage of multiple parts. Further, this will be more costly and will result in worse reliability and more difficulty placing and writing the board then will this invention. This also has the disadvantage of having asynchronous boundaries between the main bus and the rest of the chip. This can cause tough design problems and additional verification. Nevertheless, fixed relationships suffer from their own particular disadvantages. Referring to the above example, fixing relationships would, for example, result in a 1.5 to 1 relationship between the processor and the main bus oscillator. However, as the main bus oscillator is reduced, so are all of the other frequencies thereby performance by causing the one or more of the other clock frequencies to violate their required frequency ranges.
It can be seen that there is a need for a method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency.